This invention relates to a method for manufacturing an LSI (large scale integration) semiconductor device, and more specifically to a method for manufacturing a semiconductor device using a polycrystalline silicon layer doped with an impurity as an electric conductive portion such as an electrode and/or conductor.
Especially for large scale integration of an MOS (metal oxide semiconductor) type field-effect transistor (FET), an advanced technique is known where the silicon gate technology employs a polycrystalline silicon layer as a gate electrode and forms source and drain regions in the self-alignment system.
The aforesaid silicon gate technology, however, still involves too many problems to achieve further improved LSI.
Referring now to the drawings of FIG. 1, there will be described the above-mentioned problems in connection with a method for manufacturing an LSI n-channel MOS FET, by way of example. As shown in FIG. 1a, a first insulating film such as a silicon oxide (SiO.sub.2) film 2 with a thickness of approximately 1 .mu.m is formed on part of the surface of a p-type silicon substrate 1 by selectively oxidizing the surface of the substrate with the aid of e.g. a silicon nitride film mask, thereby isolating elements from one another. Then, as shown in FIG. 1b, a second insulating film such as an SiO.sub.2 film 3 as thin as about 700 A to serve as a gate oxide film is formed on part of the surface of the substrate 1 which is not covered with the SiO.sub.2 film 2 by oxidizing the surface, and a polycrystalline silicon layer 4 with a thickness of about 3,000 A is formed over the whole surface of the SiO.sub.2 film 3 by a chemical vapor deposition method, for example.
As shown in FIG. 1c, phosphorous from e.g. POCl.sub.3 as a diffusion source is diffused into the whole surface of the polycrystalline silicon layer 4 at approximately 1,000.degree. C. for about 10 minutes. A polycrystalline silicon layer 4' subjected to such phosphorous diffusion exhibits a resistance of approximately 20.OMEGA./.quadrature., as indicated by the full line of FIG. 2.
A photo-resist film 5 is formed selectively on the polycrystalline silicon layer 4' doped with the impurity, as shown in FIG. 1d, and the polycrystalline silicon layer 4' is plasma-etched for patterning by using e.g. freon plasma, and part of the polycrystalline silicon layer 4' is left to form a gate electrode.
Subsequently, as shown in FIG. 1e, n-type source and drain regions 6 and 7 are formed by removing portions of the 700 A SiO.sub.2 film 3 to form the source and drain regions, further removing the photo-resist film 5, implanting e.g. 150 kev As ions at a rate of 1.times.10.sup.16 /cm.sup.2, and annealing the resultant structure in an N.sub.2 atmosphere at approximately 1,000.degree. C. for about one hour.
Then, as shown in FIG. 1f, one or more third insulating films such as a relatively thick (about 1 .mu.m) SiO.sub.2 film 8 including phosphorus in a concentration of approximately 1.times.10.sup.21 atoms/cm.sup.3 is formed all over the surface by the chemical vapor method, and heated at a temperature of approximately 1,050.degree. C. for 20 minutes to have its surface melt. Thereafter, contact holes for leading out electrodes from the source and drain regions 6 and 7 are made in the SiO.sub.2 film 8, and aluminum layers 9a and 9b are deposited and delineated (FIG. 1g). Then, an oxide film doped with e.g. phosphorus or a PSG film 10 is formed on the Al layers, and finally a bonding-pad opening 10a is made in the PSG film 10.
As stated previously the resistance of the polycrystalline silicon layer 4' which forms the gate electrode, manufactured by the above-mentioned prior art method, is approximately 20.OMEGA./.quadrature.. This resistance value, which may be decreased as the diffusion time of impurity (phosphorus) increases as indicated by full line in FIG. 2, will never be reduced below approximately 20.OMEGA./.quadrature.. This may be attributable to the fact that the concentration of phosphorus in the polycrystalline silicon layer never increases above the solid solubility limit. Although the resistance value may substantially be halved by e.g. doubling (to approx. 6,000 A) the thickness of the polycrystalline silicon layer, the increased thickness will make it difficult to achieve accurate and fine patterning. Such a way of reducing the resistance would, therefore, be not appropriate for the formation of fine patterns, especially. When using the polycrystalline silicon layer as a conductor to transmit signals in an LSI, on the other hand, it is necessary that the resistance value of the layer be minimized to increase the operating speed of the device. The above-mentioned prior art method has not been able to fulfill those requirements.